More Cores Created a Communication Challenge
Adding processor cores increases the amount of work a computer can potentially perform at the same time. However, those cores cannot operate as completely independent machines. They must exchange information, access memory, maintain consistent copies of shared data, and communicate with other parts of the processor.
As processors become more complex, the connections between their internal components become increasingly important. A fast processing core can still lose valuable time waiting for information to arrive from another part of the chip.
AMD addressed this challenge in its Zen processor architecture with Infinity Fabric, a high-speed interconnect designed to coordinate communication between different functional blocks. Introduced with the first Ryzen processors in 2017, the technology also became an important part of AMD’s larger Threadripper and EPYC processor designs.
The central idea: Processor performance depends not only on how quickly individual cores execute instructions, but also on how efficiently those cores exchange information with caches, memory controllers, and other processing resources.
A Processor Contains Several Communication Paths
A modern CPU contains far more than arithmetic and instruction-processing circuits. Its internal organization includes cache memory, memory controllers, input/output interfaces, power-management logic, and pathways that move information between these components.
Different types of communication place different demands on the processor. Some transfers involve small control messages, while others involve substantial amounts of application data.
Processing cores exchange information when applications divide work into cooperating threads. The time required for those exchanges can influence performance.
Shared data must remain consistent when multiple cores access or modify information stored in their caches.
Processor cores request information from system memory when the required data is unavailable in nearby caches.
These activities happen continuously while a computer is operating. An effective interconnect must handle them without allowing communication delays to overwhelm the processing capabilities of the CPU.
Core Complexes Formed the Building Blocks
The original Zen architecture organized processor cores into groups known as CPU Complexes, or CCXs. Each CCX contained up to four processing cores with access to a shared 8 MB level-three cache.
In an eight-core first-generation Ryzen processor, two CCXs were connected through Infinity Fabric. This arrangement allowed AMD to combine multiple groups of cores within a single processor design.
The organization had an important consequence. Two cores within the same CCX could communicate through relatively local resources, while communication between cores in different CCXs required information to travel across the interconnect.
Both arrangements supported normal processor operation, but they did not necessarily have identical communication latency.
Distance Exists Inside a Processor
Physical separation and internal routing matter even when components occupy the same silicon chip. Information traveling between separate processing groups may encounter additional delays compared with communication that remains within one group.
Communication Latency Was Not Uniform
Latency describes the time between requesting information and receiving the response. In processor architecture, even small differences can matter because some operations depend on a sequence of exchanges before useful work can continue.
During early Ryzen testing, reviewers observed that communication between cores belonging to different CCXs could take longer than communication between cores within the same CCX.
This did not mean that every application experienced a noticeable slowdown. Programs differ considerably in how they organize work and exchange data.
Communication Within a CCX
Cores share nearby cache resources and can exchange certain information without crossing into another core complex.
Applications with closely cooperating threads may benefit when their communication remains within the same processing group.
Communication Between CCXs
Information must travel through the interconnect linking separate processing groups.
Workloads that repeatedly synchronize threads across those groups may become more sensitive to communication latency.
The distinction helps explain why two processors with similar core counts and clock speeds can behave differently when running the same software. Their internal organization can influence how efficiently applications use the available computing resources.
Memory Speed Had an Unexpected Connection
One of the notable characteristics of first-generation Ryzen processors was the relationship between system memory frequency and the operating frequency of the internal fabric.
On these processors, the fabric operated in a frequency domain linked to the memory clock. Increasing supported DDR4 memory speeds could therefore affect more than the rate at which information moved between system memory and the processor.
It could also reduce the time required for certain transfers across Infinity Fabric.
DDR4 speed terminology: DDR memory transfers data twice per clock cycle. For example, DDR4-2666 operates at approximately 1,333 MHz while providing about 2,666 million transfers per second.
On first-generation Ryzen, the relationship between the memory clock and fabric frequency made memory configuration particularly relevant to internal communication performance.
Higher memory speeds were not guaranteed to improve every program. The result depended on whether the workload was limited by memory bandwidth, memory latency, communication between core complexes, or something unrelated to those factors.
Some Applications Were More Sensitive Than Others
Programs place different demands on processor communication. A task that performs most of its calculations using data already available in local caches may be relatively insensitive to delays between processing groups.
Another application may frequently exchange information between threads, making the organization of those threads more significant.
| Workload Characteristic | Possible Performance Influence |
|---|---|
| Independent calculations | Individual cores can make progress with relatively little communication between them. |
| Frequent thread synchronization | Additional communication latency can delay dependent operations. |
| Large memory-intensive tasks | Memory bandwidth and access latency may influence processing speed. |
| Repeated access to shared data | Cache organization and data consistency traffic become more important. |
| Applications using many cores | Thread placement and the distribution of work can affect efficiency. |
These differences were particularly relevant when evaluating early Ryzen processors. Some workloads scaled efficiently across the available cores, while others responded more strongly to memory settings and communication delays.
Understanding the underlying architecture made those performance differences easier to interpret without assuming that a higher core count would automatically produce the same improvement in every application.
An important limitation: Faster memory can improve certain latency-sensitive workloads, but it cannot eliminate every delay associated with processor communication. Cache behavior, thread scheduling, application design, and other hardware characteristics remain significant.
The Same Design Extended Beyond Desktop Processors
Infinity Fabric was not limited to communication between two core complexes in a desktop Ryzen processor.
AMD also used the technology to connect multiple processor dies in larger products. This became especially important for Threadripper workstation processors and EPYC server processors introduced in 2017.
Rather than relying exclusively on one increasingly large piece of silicon, AMD could combine multiple dies within a processor package and provide communication pathways between them.
Ryzen Desktop Processors
Infinity Fabric connected internal processing groups and other functional components within the Zen architecture.
Threadripper Workstations
Multiple processor dies were combined within one package, increasing the number of available cores while introducing additional communication paths between dies.
EPYC Servers
Multiple dies provided large core counts, numerous PCI Express connections, and access to several memory channels through a coordinated processor architecture.
This approach created opportunities for scaling processor designs, but it also introduced architectural considerations involving memory locality and the time required to access resources attached to different dies.
Memory Location Became More Important in Large Systems
In a processor containing multiple dies, not every memory access necessarily follows the same physical route.
Some memory controllers are located closer to particular groups of processing cores. A request served by a nearby controller can have different latency characteristics from one that must travel across an additional interconnect.
This distinction is particularly relevant to non-uniform memory access, or NUMA, where the time required to access memory depends partly on the relationship between the requesting processor and the memory location.
Architecture Detail
Local memory access: A processing core reaches memory through a controller associated with its nearby processing resources.
Remote memory access: The request crosses an additional connection to reach memory associated with another processing die or NUMA node.
Practical consequence: Applications that frequently access remote memory may experience additional latency, even when the processor has sufficient overall memory capacity and bandwidth.
Operating systems and applications can account for these differences by considering processor topology and memory placement. Such decisions become increasingly valuable as the number of cores, dies, and memory channels grows.
Processor Connections Became Part of the Performance Equation
Infinity Fabric illustrated an important shift in processor design. Increasing performance was no longer simply a matter of adding faster cores or expanding cache capacity. The communication system connecting those resources also needed to support the growing complexity of the processor.
For desktop users, the effects could appear in differences between application workloads or in the performance changes associated with memory configuration. For workstation and server systems, the same architectural principles influenced how processors could scale across multiple dies and large numbers of cores.
The introduction of Infinity Fabric in 2017 demonstrated that the pathways inside a processor were becoming just as important to understand as the processing units themselves. Core count and clock speed remained useful specifications, but they could not describe the complete performance characteristics of an increasingly interconnected CPU.
